MIPS is an instruction set developed by Sony, Nintendo, and NEC. MIPS, which stands for Million Instructions Per Second, is a rating of a Central Processing Unit (CPU), that refers to how many low-level machine code instructions a processor can execute in one second. The core MIPS instruction set architecture determines many aspects of the implementation, which includes an integer arithmetic-logic instruction, the memory-reference instructions, and the branch instructions. Much of what needs to be done to implement these instructions is the same, independent of the exact class of instruction.
In this project we have developed software for simulation a multi-cycle and single cycle MIPS processor.
The multi-cycle data-path split the execution of the instruction into stages, each stage is done in one clock cycle, which make the hardware be shared through the stages, this allow to use less hardware for implementing the processor, while the single cycle all the instruction being executed in one clock cycle.